The present invention relates generally to semiconductor devices, and more particularly, to high-speed receiver semiconductor devices. Still more particularly, the present invention relates to the circuit and method of using thin and thick film gate oxide MOSFETs to construct wide common mode, high-speed differential receivers, in deep sub-micron technology semiconductor devices.
Differential signaling has been utilized for many years as a data transmission method. A differential receiver converts and amplifies a differential input signal (IN+ and IN−) to a differential output signal (VOUT+ and VOUT−). These receivers offer high data transmission speeds, low noise coupling, and low EMI (electromagnetic interference). For embodiment, teletype equipment was some of the first types of equipment to use differential signaling to communicate. Today, computers often communicate between ports by low voltage differential signal (LVDS) drivers and receiver pairs. In addition to the LVDS data transmission technology, emitter coupled logic (ECL), common mode logic (CML), and hyper-transport (high-bandwidth chip-to-chip technology) technology are utilized for data transmission methods. Typical differential signal transmission speeds are over 100 Mbps (mega bits per second). In each of these transmission methods, high speed, wide common mode, voltage differential receivers are necessary building blocks to attain the required data transmission speeds while meeting the low noise coupling, and the low EMI requirements.
Semiconductor technology is evolving into the deep sub-micron geometries of less than 100 nanometers (nm). This technology is needed to produce today's portable devices such as cellular telephones, laptops, and other portable electronic devices. The smaller geometry gates of less than 100 nm offer more complex functionality and higher performance, but not without a cost. As the nanometer gate geometry becomes smaller, its power dissipation increases dramatically, hence the battery power drain increases significantly.
Conventional wide common mode, high-speed differential receivers utilize thick gate oxide MOSFETs in deep sub-micron technology devices for all required series amplifier stages. Each of these stages is designed to operate from high voltage power supplies (VDDH) of approximately 3.3VDC to maximize data transmission speeds. A final translation stage must be implemented to convert the 3.3VDC (VDDH) supply voltage to 1.2VDC (VDDL) to interface with the subsequent digital logic devices using the 1.2VDC (VDDL) supply voltage. These multiple high-speed receiver amplifier stages that use the VDDH supply voltage dissipate much more power than receivers that use the VDDL supply voltage.
Desirable in the art of wide common mode, high-speed receiver designs are additional designs that reduce power dissipation while still meeting or exceeding the high-speed data transmission requirements.